`include "define.v"

module pc_reg (
    input wire rst,
    input wire clk,
    input wire[`StallBus] stall,
    input wire branch_flag_i,
    input wire[`RegBus] branch_addr_i,
    input wire                    flush,
	input wire[`RegBus]           new_pc,
    output reg[`InstAddrBus] pc,
    output reg ce
);
    always @ (posedge clk) begin
        if (rst == `RstEnable) begin
            ce <= `ChipDisable;
        end else begin
            ce <= `ChipEnable;
        end
    end

    always @ (posedge clk) begin
        if (ce == `ChipEnable) begin
            if (flush == 1'b1) begin
                pc <= new_pc;
            end else if (stall[0] == `NoStop) begin
                if (branch_flag_i == `Branch) begin
                    pc <= branch_addr_i;
                end else begin
                    pc <= pc + 4'h4;
                end
            end
        end else begin
            pc <= 32'h00000000;
        end
    end

endmodule
